1. Field of the Invention
The present invention relates to a layout of conductive lines having a pattern of a line & space, for instance, which is used for a semiconductor memory with a large memory capacity.
2. Description of the Related Art
In recent years, many electronic apparatuses using a NAND-type flash memory as a main memory have been commercialized. On the other hand, an increase of storage capacity of the NAND-type flash memory becomes a problem as the function of the electronic apparatus increases.
When achieving the increase of the storage capacity, chip layout is very important. For instance, although miniaturization of the memory cell has progressed remarkably, in order to achieve improvement of reliability while eliminating problems such as disconnection, short circuit, or the like of conductive lines, size or pitch of the conductive lines or contact holes should be determined in consideration of deviation of alignment in a photolithography (Jpn. Pat. Appln. KOKAI Publication No. 2002-151601).
In particular, even though word lines are formed with minimum processing size (feature size) by a pattern of line & space, in order to connect the word lines with a word line driver, for instance, it becomes necessary to provide connecting lines made of metal. Therefore, investigation of a layout of a connecting area connecting the word lines and the connecting lines is indispensable for reduction of a chip size, and further for an increase of storage capacity.
Similarly, such problem occurs to a semiconductor memory with a large memory capacity in addition to the NAND-type flash memory.